• Left panel: Hierarchy (drawn levels and the tree of placed cells), Layers, and the options of the current tool.
• Toolbar: undo / redo, the tools (Select, Stretch, Move, Copy, Rectangle, Polygon, Path, Label, Via, Instance, Chop, Ruler), fit, Zoom box, Prev view, Grid, Snap, Gravity, DRD, Constraints, Magnet, Live DRC, Flylines, and GDS to export the cell.
• Status bar: X / Y of the cursor; while a command is in progress dX, dY and Dist from its reference point; Sel: n (Sel(P): n for a partial selection); Cmd: the current tool; and a mouse L: … M: … R: … line telling what each button does now.
• Right panel: cell statistics or the inspector, Edit operations, Layer operations, and the verification sections (see Verification).

Layers

• Click a layer row to make it the active layer; new shapes are drawn on it.
• Click the eye to show or hide a layer. Click the small box left of the eye to make a layer selectable or not: shapes on non-selectable (or hidden) layers are drawn but cannot be picked, like Virtuoso’s LSW. AV / NV show / hide every layer, AS / NS make every layer selectable / not.
• Filter narrows the list by name; Instances selectable controls whether placed cells can be picked.
• Each row shows the fill pattern, the name and the GDS layer/datatype. Hover a row to see its minimum width and spacing.

Drawing

Keys act on the canvas only while the mouse is over it.

While drawing a polygon or path, Backspace removes the last point and Esc cancels.

• Gravity (on by default, G toggles) snaps the cursor to vertices (diamond marker) and edges (circle marker) of nearby shapes and instance boxes, so new geometry abuts exactly.

• DRD (design-rule-driven editing, on by default) shows the minimum-spacing halo of a rectangle being drawn and marks in red every gap to a same-layer shape that is closer than the minimum spacing, and shapes narrower than the minimum width. It works while drawing rectangles and paths, moving, copying and pasting. Neighbours inside placed cells count too (at any depth), as do the shapes around a cell edited in place; a moved or pasted instance is checked by the shapes along its outline.

• Magnet (on by default) pulls a shape being drawn or moved to exactly the minimum spacing from its neighbours when it comes close.

• Live DRC (on by default) checks the rule deck around every edit; see Live DRC.

• Layer tap: T makes the layer of the shape under the cursor the active layer.

• Changing metal while routing: with the Path tool, press + (or = / PageUp) to end the path at the cursor, drop the via to the routing layer above and continue on it; - (or PageDown) goes down.

• Polygons are Manhattan by default: each point is aligned horizontally or vertically to the previous one. Hold Shift (or Ctrl) while clicking for any angle. The closing edge gets an extra corner so a Manhattan outline stays Manhattan.

• Paths are always Manhattan. Width (nm) in the left panel sets the width; 0 uses the layer’s minimum width. Path ends are extended by half the width.

• Labels on a routing layer name the net under them (used by extraction and LVS).

• Vias come from the technology (bottom layer, cut, top layer); dragging an area fills it with as many cuts as fit.

Rectangle step by step

1. Click the metal1 row in Layers.
2. Press R and drag on the canvas.
3. Press Esc to return to Select, click the rectangle and type exact coordinates in the inspector (x0, y0, x1, y1 in µm).

Selecting and editing

Partial selection

F4 (or Edit > Toggle Partial Select) toggles partial selection. In Select, a click near an edge selects that edge (both its vertices) or a vertex; Shift+click adds or removes; a drag box selects the vertices inside it (items entirely inside are taken whole). Selected edges and vertices are highlighted and the status bar shows Sel(P): n.

Press S, click a reference point, then the destination: every selected vertex moves, and Manhattan shapes stay Manhattan (adjacent edges slide along). Dragging a partially selected shape in Select stretches it too. Esc clears the partial selection.

Forms

Each key opens a floating form and closes it again:

The Edit section of the right panel (shown when something is selected) also has:

• Flatten: replace the selected instances with their contents (one level).
• Make cell: move the selection into a new cell and place an instance of it.
• Merge: union the selected shapes per layer.
• Size with Apply: grow (positive µm) or shrink (negative) the selected shapes.
• Align (two or more items): align left, centre or right edges, bottom, centre or top edges; Space X / Space Y spread three or more items with equal gaps.

Navigation

These are the Virtuoso interaction profile, the default. With Conventional (Settings > Interaction) the wheel zooms and a right drag pans.

Bindkeys go to the canvas while the mouse is over it, and stay with it while one of its forms (q, F3, e, Shift+E) is open on top, until you click elsewhere in the window. A text field being typed in, or a focused control in a form under the mouse, gets the keys first.

Layer operations

With nothing selected, Layer operations computes Boolean results:

1. Choose layer A, an Operation (AND, OR, NOT, XOR, SIZE) and layer B (or a distance By in µm for SIZE).
2. Choose the Output layer.
3. Keep Include hierarchy (flattened) checked to include placed cells.
4. Press Run. The result shapes are added to the output layer and selected.

Boolean operations, Merge, Size and Chop handle any-angle geometry (45° and arbitrary edges, from GDS / OASIS or the polygon tool) exactly. Crossings that fall between grid points snap to the nearest database unit. When sizing, horizontal, vertical and 45° edges move by the given distance and corners of 90° or more stay sharp. Results with holes are cut into hole-free polygons.

Constraints, compaction and compare

These commands have no menu or bindkey; run them from the command palette, where they are listed as “Layout Assist: ”.

• Symmetric About Vertical / Horizontal Axis, Keep Left / Bottom Edges Aligned, Keep Centres Aligned Vertically / Horizontally and Fix In Place add a constraint to the selected items. Moving one member moves the others so the constraint keeps holding. Infer Constraints From Schematic adds symmetry constraints for the schematic’s matched devices; Remove Constraints clears them. The Constraints checkbox in the toolbar draws them, and the Constraints section of the right panel lists them, with Snap for one that no longer holds.
• Compact (Left, Then Down) and Compact Left / Right / Down / Up slide the cell’s top-level items toward one side as far as the spacing rules allow. Connected geometry and the members of a constraint move together.
• Compare With Saved and Compare With Git HEAD draw the geometry added and removed since the last save or the last commit; Next Difference steps through them.

Hierarchy

Placing a cell or an array

1. Press I. The left panel lists PCell variants and Place cell (every other cell with a layout that would not create a cycle).
2. Pick a cell, set Rotation, Mirror about x, Columns and Rows. Array elements abut at the cell’s extent.
3. Click to place.

Select an instance to edit its position, rotation and mirroring in the inspector. Check Array to turn it into an array (GDS AREF) with Columns, Rows, Column pitch and Row pitch.

Drawn depth

The levels field in Hierarchy (keys 0 to 8, and 9 for all levels) sets how many levels of placed cells are drawn with their contents (Shift+F all levels, Ctrl+F top level only). Deeper instances are drawn as labelled boxes. Missing cells are drawn in red.

Large designs stay fast: cells that are small on screen collapse to boxes and tiny shapes to dots.

The hierarchy tree (Edit > Hierarchy Tree, Shift+T) lists the cells placed in the current cell with their counts; click one to open it. Tools > Hierarchy Browser shows the whole project’s layout hierarchy with where-used lists (see Tools).

Generators and fill

The Tools menu also adds geometry to the active layout, each as one undoable step:

• Layout Generators > Guard Ring: a p+ substrate or n+ nwell ring with contacts and a metal1 strap around an area or the selection;
• Layout Generators > Via Array: via arrays on every overlap of two layers, or filling an area;
• Layout Generators > Matched Placement: common-centroid, interdigitated or 2-D common-centroid placement of matched transistors with dummies;
• Layout Generators > By Example: place the devices like a finished cell with the same circuit (matched by topology), copying its wells, implants and taps, and optionally route;
• Dummy Fill: fill squares to meet a density rule.

See Tools for the options.

PCells

Parametric cells are generated from the technology and stored as ordinary cells in the pcells library (for example nmos_w1000_l180_nf2).

Device appears when the technology is a PDK with several MOS devices of that polarity (for example low- and high-Vt variants): the PCell then draws that device’s marker layers, and the variant name ends with the device name. The default is the PDK’s first device.

To place one, press I, choose the PCell in the left panel, set its parameters and click. To change a placed PCell, select it, edit the parameters in the PCell section of the inspector and press Apply. Well and substrate taps (ntap, ptap) are created by schematic-driven layout; their parameters can be edited in the inspector the same way.

SKILL scripts

Tools > Load SKILL (.il) runs a Cadence SKILL file on the project; ics skill and the MCP tool run_skill do the same from the command line and from agents. Printed output goes to the log, every changed layout can be undone, and geGetEditCellView() returns the cell open in the editor.

The CIW tab of the bottom panel (Tools > SKILL CIW, or “CIW” in the command palette) is an interactive SKILL prompt like Virtuoso’s Command Interpreter Window. Variables, procedures and open cellviews persist between commands and include everything defined by files loaded with Tools > Load SKILL; opening another project starts a fresh session. Enter runs the line, a line with unclosed parentheses or strings continues on the next one (the prompt shows ...), and Up / Down recall earlier commands.

cv = dbOpenCellViewByType("work" "pad" "layout" "maskLayout" "w")
for(i 0 3
  dbCreateRect(cv list("metal1" "drawing") list(i*2:0 i*2+1:1)))
dbCreateInstByMasterName(cv "work" "via_cell" "layout" "I0" 0:5 "R90")
printf("%d shapes\n" length(cv~>shapes))

Supported:

• syntax: C style f(a b) and Lisp (f a b) calls, infix operators, x:y points, obj~>prop, tbl[key], 'quote, ?key arguments, ; and /* */ comments, scale factors such as 1.5u;
• control: if / then / else, when, unless, cond, case, while, for, foreach (also mapcar and tables), let, prog / return, setof, exists, errset, error;
• procedure / defun with @optional, @key, @rest, lambda, funcall, apply, mapcar, load; list, string, math and printf / sprintf built-ins, makeTable tables and disembodied property lists;
• layout: dbOpenCellViewByType ("r", "w" clears the layout, "a" appends; libraries and cells are created on demand), dbCreateRect, dbCreatePolygon, dbCreatePath, dbCreateLabel, dbCreateInst, dbCreateInstByMasterName, dbCreateSimpleMosaic, dbDeleteObject, dbMoveFig, dbCopyFig, dbFindAnyInstByName, dbGetOverlaps, dbTransformPoint / dbTransformBBox; layer Boolean operations dbLayerAnd, dbLayerOr, dbLayerXor, dbLayerAndNot (cv layer shapes1 shapes2) and dbLayerSize (cv layer shapes size), which add the result to layer and return the new shapes (any-angle geometry included); dbSave and dbClose do nothing (save the project). Shape, instance and cellview properties (bBox, points, layerName, xy, orient, shapes, instances, …) can be read, and the geometric ones set.

Coordinates are in µm. A layer is a name, list(name purpose) or a layer index; a purpose other than drawing first looks for a layer named name.purpose or name_purpose. Variables are dynamically scoped as in .il files. Not supported: schematic views, PCell definitions (pcDefinePCell), interactive hi* / le* forms and SKILL++ (.ils) lexical scoping.

GDSII

• File > Import > GDSII / OASIS… reads a GDS or OASIS file into a new library with full hierarchy.
• GDS in the toolbar or File > Export > Cell GDSII… writes the cell and every cell it places; Export > Library GDSII… writes every layout in the project. Cell OASIS… and Library OASIS… write OASIS instead.

Layers are mapped by GDS layer / datatype. Layers the technology does not have are added to it on import, so nothing is lost. A stream layer map (Tools > Stream Layer Map, or a Virtuoso layer map file) renumbers layers on export, maps other numbers onto technology layers on import, or drops them.

Verification: DRC, extraction and LVS

The verification tools are in the Verify menu and in the right panel of the Layout workspace. They run in the background on the flattened layout of the active cell; while one runs, the panel shows its progress and a Cancel button. After you edit the layout, the panel notes that results are out of date.

Design rule check (DRC)

1. Open the cell’s layout.
2. Press Run DRC in the Design Rule Check section (or Verify > Run DRC).
3. The result is either No violations or a list grouped by rule, with a count per rule. Markers are drawn on the canvas.
4. Expand a rule to see its description and the violation locations; click one to zoom to it.
5. Clear removes the results and markers.

The rules come from the technology’s deck. Expand Rule deck to view and edit it in place: Run DRC uses the edited text right away, Save to technology stores it in the project’s tech.json, and Reset replaces it with the deck derived from the technology’s layer and via rules. Syntax errors are listed by line. See Technology for the deck syntax. Rule Designer… (also Tools > DRC Rule Designer) edits the deck as forms and self-tests every rule on generated patterns; see DRC Rule Designer.

A layer that fails a density rule can be filled with Tools > Dummy Fill (see Dummy Fill).

DRC checks Manhattan geometry; other shapes are skipped and counted. Distances between corners are Euclidean.

Live DRC

The Live DRC checkbox in the layout toolbar re-checks the deck around every edit in the background and draws the violations as dashed boxes as they appear; hover one to see its rule. Quick Fix (Ctrl+.) on a violation offers candidate edits of top-level shapes (reshape, move or add), each checked with DRC first and marked clean or with the number of new violations it causes; it turns live DRC on when it is off. Fix All Violations (command palette) applies fixes until none helps any more, as one undoable step. Geometry inside placed cells is not changed.

Connectivity extraction

1. Press Extract in the Connectivity section (or Verify > Extract Nets).
2. The summary shows the number of nets and NMOS / PMOS transistors.
3. Click a net in Nets to highlight it. Check Pick nets and click a shape on the canvas to highlight the net it belongs to.
4. Devices lists each transistor with W, L and its terminal nets; click one to zoom to its gate.

Tools > Net Browser lists the extracted nets in a sortable table with their layers, area, transistor terminals and wire capacitance; click one to highlight it and zoom to it (see Net Browser).

How the extractor works:

• Conducting layers are the layers joined by vias. Diffusion is active minus poly.
• A transistor is poly over active. It is PMOS when it is inside pplus (or inside nwell when there is no implant). L is measured across the gate; W is area / L.
• Net names come from labels in the top cell on conducting layers. Unnamed nets are called netN.
• Warnings report labels not on conducting geometry, two labels shorted together, and a label on several unconnected pieces.

Layout versus schematic (LVS)

1. The cell needs both a schematic and a layout. Device names do not have to match, but labels on the layout’s pins (in, out, vdd, …) help: equal net names anchor the comparison.

2. Press Run LVS (or Verify > Run LVS).

3. The result is Layout matches schematic or a list of differences, each tagged:

   • [missing]: a schematic device not found in the layout,
   • [extra]: a layout device not in the schematic,
   • [param]: W or L differ by more than 1 %,
   • [net]: a net whose connections differ.

   Click a difference with a location to zoom to it.

Comparison rules:

• Only MOS transistors are compared. Voltage and current sources are ignored; other schematic devices (R, C, diodes) are reported as not extracted.
• Parallel devices with the same terminals and L are merged and their widths summed, so multi-finger layouts match single schematic devices; the schematic m multiplies W.
• Bulk terminals are ignored.
• Devices that are always off (gate tied to bulk), such as dummy fingers, are dropped.
• Net names are compared case-insensitively; 0, gnd and vss are treated as the same.

The demo cell cmos_inverter deliberately has LVS findings (a PMOS width and the load capacitor); nand2, nor2, ring_osc5, current_mirror, ota5t, sram6t, aps3t, full_adder and ota2s are clean.

Sign-off with external tools

The built-in checks are fast and good for iterating. For sign-off, a technology can list runsets that run a foundry or PDK deck in an external tool:

In the Layout workspace, the Sign-off section appears when the technology has runsets. Pick a Runset and press Run (or Verify > Run Sign-off Runset). IC Studio writes the cell and every cell it places to <cell>.gds in a new temporary folder, plus the schematic as a .subckt for LVS, runs the tool there and reads its report:

• DRC violations appear as markers on the canvas, like the built-in DRC. Violations the tool reports inside sub-cells keep sub-cell coordinates and name the cell.
• LVS shows whether the layout matches and the tool’s messages.
• The folder (shown under the result) keeps the inputs, reports and the tool’s log.

How each tool is called:

• KLayout: klayout -b -r DECK -rd input=CELL.gds -rd topcell=CELL -rd report=FILE, plus -rd schematic=CELL_sch.cir for LVS and the runset’s vars. The variable names can be changed with klayout = { input = "...", topcell = "...", report = "...", schematic = "..." }.
• Calibre: a control file sets LAYOUT PATH, LAYOUT PRIMARY, LAYOUT SYSTEM, the ASCII results database (DRC) or SOURCE PATH / LVS REPORT (LVS), adds #DEFINE for each var and INCLUDEs the deck. The deck itself must not set these statements. Then calibre -drc -hier or calibre -lvs -hier -spice.
• netgen: netgen -batch lvs "CELL_lay.cir CELL" "CELL_sch.cir CELL" SETUP REPORT.

The schematic netlist leaves out the element letters in the runset’s skip (default V and I) and names the ground net ground (default gnd). Executables are found on the usual install paths and PATH; set ICS_KLAYOUT, ICS_CALIBRE or ICS_NETGEN to override them.

Runsets come from a PDK file ([[signoff]]) or the signoff array in tech.json:

"signoff": [
  {"name": "KLayout DRC", "tool": "klayout", "check": "drc", "deck": "/pdk/rules.drc",
   "vars": {"feol": "true"}},
  {"name": "Calibre LVS", "tool": "calibre", "check": "lvs", "deck": "/pdk/calibre.lvs",
   "skip": ["V", "I", "C"]}
]

From the command line

ics drc myproj nand2 [--deck rules.drc]   # exit code 1 on violations
ics extract myproj nand2                  # extracted SPICE netlist
ics lvs myproj nand2                      # exit code 1 on differences
ics signoff myproj nand2                  # list the sign-off runsets
ics signoff myproj nand2 "KLayout DRC"    # run one; exit code 1 on violations / mismatch

These exit codes make the checks usable in CI. See Command line.

Schematic-driven layout

IC Studio can build a layout from a schematic: it places the transistors as PCells, shows the connections still to be made as flylines, and routes them.

Step by step

1. Draw and simulate the schematic. Give the external nets labels (in, out, …); use the Ground and Supply symbols for the rails.
2. With the cell active, choose Verify > Generate Layout from Schematic. The cell gets a layout view if it has none, and the Layout workspace opens with flylines on.
3. Inspect the placement. Move devices if you want; their names keep the link to the schematic.
4. Choose Verify > Route Flylines to route the remaining connections.
5. Add pin labels on metal for the external nets (Label tool, L) so that LVS can anchor them.
6. Run DRC and LVS (see Verification), then simulate with Include layout parasitics.

Each step can be undone with Ctrl+Z. The console lists what was placed, skipped, matched and routed.

Demo: auto P&R

The demo cells full_adder (28 transistors) and ota2s (two-stage OTA with a common-centroid input pair and mirror) have layouts made only by this flow. Clear one (Ctrl+A, Delete) and run the two commands above to watch it happen. The demo gallery has a complete script.

Placement

• Each NMOS and PMOS becomes a PCell instance named after the schematic device (M1). W and L come from the device’s w and l parameters; m multiplies the device. Devices wider than 5 µm are split into fingers. With a PDK, the schematic model selects the PCell’s device (and its marker layers, such as lvtn for a low-Vt model).
• PMOS devices form a row above the NMOS row, gates facing the channel between the rows.
• Neighbouring devices of the same type and width that share a source / drain net are abutted with shared diffusion.
• Wells and implants are merged across each row, and each row ends with a bulk tap (ntap in the PMOS row, ptap in the NMOS row) on the row’s bulk net.
• Devices already in the layout (by name) are left alone, so you can generate again after adding devices to the schematic.
• Devices without a layout generator (R, C, L, diodes, sources) are skipped and listed in the console.

Matched devices

Differential pairs and current mirrors are detected automatically:

• Differential pair: two devices of the same type, W, L and m with a common source net that is not a rail, and different gates and drains.
• Current mirror: devices of the same type and L with a common gate and source, where the gate is tied to one device’s drain.

You can also group devices explicitly by giving them the same match parameter, or opt a device out with match=none. The inspector shows only the standard parameters, so add match (and match_rows) to the device’s params in the cell’s schematic.json:

"params": { "model": "nmos", "w": "4u", "l": "500n", "m": "1", "match": "pair1" }

A matched group is split into equal unit fingers named <device>.<k> (for example M1.1, M1.2), placed in common-centroid order (ABBA). Groups of 8 units or more, or groups with match_rows=2, use two cross-coupled rows (ABBA / BAAB); match_rows=1 forces a single row. Each unit row is closed by dummy fingers at both ends whose gates are tied to bulk; LVS ignores them because they are always off.

The console reports each group, for example A, B: matched as ABBA (A = M1, B = M2), or why it could not be matched.

Flylines

The Flylines checkbox in the layout toolbar draws a dashed line, labelled with the net name, for every schematic connection that is not yet made in the layout. They update after every edit, so you can route by hand and watch them disappear.

Router

Route Flylines runs a maze router (A* search) over the routing metal layers above poly (metal1, metal2 and metal3 in the generic technology):

• The routing grid is aligned to the device terminals; wires have one width that fits a via, with DRC spacing between tracks.
• Existing geometry is avoided. Short nets are routed first; nets that block each other are ripped up and rerouted.
• Metal1 is expensive and each higher layer has a preferred direction, so long runs move to upper metals.

Every named schematic net (labels and supplies; the ground symbol becomes gnd) that is fully connected after routing gets a text label at one of its terminals, unless the top cell already has a label of that name. The label goes on the first metal, or on the layer the PDK names for its net labels ([[pin_label]], e.g. Metal1.text in SG13G2), so external LVS decks see the layout’s ports with their schematic names.

The console summary gives the routed nets, connections, vias and rip-ups. Nets that could not be routed stay as flylines with a reason (terminals not on conducting geometry, or pieces not reached). Finish them by hand and route again.

Cross-probing

Select a device in the schematic and switch to the layout: the instances with the same name (including its unit fingers) are selected, and the other way round.

From the command line or an agent

ics route myproj nand2 --place   # place missing devices, route, save; exit 1 if nets remain

The MCP server offers generate_layout, flylines and route (see MCP server).

Technology

The technology (PDK) of a project lives in tech.json in the project folder. It defines the layers, their GDS numbers and display style, simple width / spacing rules, vias, electrical coefficients for parasitic extraction, and the DRC rule deck. A project without tech.json uses the built-in generic180 technology.

generic180

A generic 180 nm-class technology, used by new projects and the demo. 1 dbu = 1 nm, grid 10 nm.

Routing layers are poly and metal1 to metal3. Vias: contact (active to metal1), polycon (poly to metal1), via1, via2.

tech.json

Top level:

Layer:

{
  "name": "metal1", "gds_layer": 7, "gds_datatype": 0,
  "color": [80, 140, 255, 160], "fill": "hatch",
  "min_width": 230, "min_spacing": 230, "routing": true
}

• fill: solid, hatch, backhatch, cross, dots or outline.
• min_width, min_spacing: in dbu; 0 means not checked. min_area (optional): in dbu²; PCell contact plates and router via pads grow to reach it.
• routing: a routing layer carries net labels and is used by extraction and the router.

Via: name, bottom, cut, top (layer names), cut_size, cut_spacing, enc_bottom, enc_top (dbu) and resistance (Ω per cut).

Parasitic coefficients (caps), one entry per layer: layer, area (aF/µm²), fringe (aF/µm of edge), coupling (aF; adds coupling * length / spacing for a parallel neighbour) and resistance (Ω per square).

DRC rule deck

The deck is plain text, one statement per line. # starts a comment. Lengths are in µm, areas in µm². Keywords and layer names are not case sensitive. Every rule can have an optional NAME: prefix; otherwise a name such as metal1.W or contact.EN.metal1 is generated. A #@ text line gives the next rule its description, reported with its violations instead of the generated one.

Rules

Derived layers

NAME = A and B
NAME = A or B
NAME = A not B        # A minus B
NAME = A xor B
NAME = A size DIST    # grow (negative DIST shrinks)
NAME = A wide MIN     # the parts of A at least MIN wide
NAME = A interact B   # pieces of A that overlap or touch B
NAME = A inside B     # pieces of A entirely inside B
NAME = A outside B    # pieces of A that do not overlap B
NAME = A enclose B    # pieces of A that contain a whole piece of B
NAME = A touch B      # pieces of A that touch B without overlapping it
NAME = A not interact B   # (also not inside, not outside, not enclose, not touch)
NAME = A area MIN MAX # pieces with MIN <= area < MAX (µm²; MAX may be inf)
NAME = holes A        # the enclosed empty areas of each piece of A
NAME = extents A      # the bounding box of each piece of A

A piece is an edge-connected part of a layer. Derived layers can use technology layers and derived layers defined earlier, and can be used in any rule. With flag, any derived layer becomes a check, for example floating poly:

floating = poly not interact active
PO.FLOAT: flag floating

SVRF decks

A deck written in SVRF (the Calibre rule language) is recognised and translated to these rules, so a foundry-style deck runs on the built-in engine. It works everywhere a deck is used: the Rule deck editor, drc_deck in tech.json or a PDK file, ics drc --deck rules.svrf, and runsets with tool = "builtin". From a file, INCLUDEs are resolved relative to it.

Translated:

• Comments, #DEFINE / #UNDEFINE / #IFDEF / #IFNDEF / #ELSE / #ENDIF, numeric VARIABLEs.
• LAYER MAP g DATATYPE d n and LAYER name n .... A layer number maps to the technology layers with that GDS layer and datatype (any datatype without a LAYER MAP).
• Layer operations AND, OR, NOT, XOR, [NOT] INTERACT / INSIDE / OUTSIDE / ENCLOSE / TOUCH, SIZE a BY d [OVERUNDER | UNDEROVER], HOLES, EXTENTS, COPY, AREA, and parentheses.
• Rule checks NAME { @ comment ... } with INT a < d (width), EXT a < d (space), EXT a b < d (separation), ENC a b < d (enclosure), AREA a < x, DENSITY a < x | > x WINDOW w STEP s, or any layer expression (all of its geometry is reported). The @ comment becomes the violation’s description.

Specification and LVS statements (LAYOUT, DRC, PRECISION, CONNECT, DEVICE, …) are skipped. Check modifiers that change the measurement (OPPOSITE, PROJECTING, PARALLEL, …) are ignored with a note; those that only shape the output (REGION, SINGULAR, ABUT) silently. Anything else, such as edge operations, WITH WIDTH or two-layer INT, leaves its rule check out. Every such case is listed with its line number: in the SVRF notes under the rule deck, as note: lines from ics drc, and as deck_notes from MCP. The built-in measurements are Manhattan and Euclidean at corners, so for sign-off run the same deck in Calibre (see Verification).

Example

# poly and gates
width poly 0.18
space poly 0.24
gate = poly and active
GATE.EX: extension poly active 0.22
width gate 0.18

# metal1, with a larger spacing next to wide metal
width metal1 0.23
space metal1 0.23
m1w = metal1 wide 10
M1.WIDE.S: separation m1w metal1 0.6
area metal1 0.2

# contacts and vias
enclosure contact active 0.1
enclosure contact metal1 0.06
enclosure via1 metal1 0.06

antenna metal1 400
density metal1 20 80 100

When a technology has no drc_deck, IC Studio derives one from the layers’ min_width, min_spacing and min_area, the via cut sizes, spacings and enclosures, a poly-over-active extension, antenna rules and the PDK’s drc_extra lines. Open Rule deck in the Layout workspace to see it, edit it, and Save to technology. The DRC Rule Designer edits the same deck as forms. The command line can use a separate file: ics drc <project> <cell> --deck rules.drc.

PDK files

A PDK file is one TOML file that describes a whole process: layers with their rules, vias, the layer roles, the MOS devices and the SPICE model library. The repository includes pdks/sky130A.toml (SkyWater SKY130) and pdks/ihp-sg13g2.toml (IHP SG13G2, 1.2 V and 3.3 V MOS devices, Metal1 to TopMetal2). Both read the models and sign-off decks from an installed PDK through $PDK_ROOT.

• GUI: File > Import > PDK… (or Load PDK… in the command palette)
• CLI: ics load-pdk myproj pdks/sky130A.toml
• MCP: the load_pdk tool

Lengths in the file are in µm. Relative paths are relative to the PDK file, and ${VAR} expands an environment variable, so the model library can point into an installed PDK:

[models]
path = "${PDK_ROOT}/sky130A/libs.tech/ngspice/sky130.lib.spice"
corners = ["tt", "ff", "ss", "sf", "fs"]
default = "tt"
length_unit = "um"   # the models take W / L in µm

The main sections:

What changes with a PDK:

• Extraction finds gates on the role layers and names each transistor after the first [[device]] of its polarity whose layers all cover the gate and whose exclude layers do not (for example lvtn for low-Vt devices).
• Netlists map the schematic models nmos / pmos to the first device of each polarity, write X elements for subckt devices, and load the model library with .lib at the corner chosen in the Simulation workspace. PDK models need ngspice.
• LVS also compares device models.
• PCells, schematic-driven layout and routing use the role layers, vias and rules. PCell variants already in the project are regenerated.
• MOS PCells can be any [[device]] of the PDK and then draw its marker layers (e.g. lvtn around a low-Vt device, marker_enc beyond the diffusion). Schematic-driven layout picks the device from the schematic model, so a low-Vt transistor in the schematic is placed, extracted and compared as that device. [[pcell_layer]] adds layers such as SKY130’s npc over poly contacts:

drc_extra = [
  "pcon = licon1 and poly",
  "pcon_npc = npc size -0.1",
  "pcon_bad = pcon not inside pcon_npc",
  "NPC.EN: flag pcon_bad",
]

[[pcell_layer]]
layer = "npc"
around = "poly_contact"
enc = 0.1

The contact to gate spacing grows when needed so that neighbouring source / drain contacts keep the first metal’s spacing at short gate lengths.

Importing a real PDK layer set

IC Studio reads KLayout layer properties (.lyp) and, optionally, the KLayout technology file (.lyt):

• GUI: File > Import > KLayout layer properties…
• CLI: ics import-tech myproj sky130A.lyp --lyt sky130A.lyt

What is imported:

• Every layer entry with a concrete layer/datatype source becomes a layer. Its name comes from the entry’s name (spaces become _, duplicates get _2, _3, …).
• Colours come from the fill or frame colour; KLayout dither patterns map to the nearest fill style.
• Layers named like poly, li, met1, metal2, m3 are marked as routing layers.
• From the .lyt: the technology name, the database unit and the default grid.

Not imported: width / spacing rules, vias, parasitic coefficients and a DRC deck. Add them to tech.json (and the deck in the Rule deck editor) to use DRC, extraction and routing with that technology.

Existing layouts are kept: shapes move to the new layer with the same GDS layer / datatype (or the same name), layers in use that the file lacks are kept, and coordinates are rescaled if the database unit changes.

Tools

The Tools menu collects the sub-tools, modelled on their Cadence Virtuoso counterparts. Each opens as a window docked inside the main window and works on the project open there, usually on the active cell. The pop-out button left of a window’s close button moves it into its own OS window, and Dock in that window brings it back; the choice is remembered per tool. Every tool is also in the command palette (Ctrl+K).

Waveform Calculator

Tools > Waveform Calculator (also Simulation > Waveform Calculator) evaluates expressions on the active cell’s simulation results.

1. Simulate the cell (F5), then open the calculator.
2. Pick the Dataset (op, dc, ac, tran).
3. Type an expression, or click a signal or a function on the left to insert it.
4. Evaluate (or Enter) shows the result in Results: a number for measurements, or the point count of a waveform. Plot adds a waveform to the Simulation plot as a new signal named after the expression.

Plotted expressions are evaluated again after every simulation run, so they stay on the plot. Click an expression in Results to edit it again.

Expressions use + - * / ^, parentheses and numbers with SPICE suffixes (1n, 10k, 2meg). Signals are v(node), v(a,b) (= v(a) - v(b)), i(source) or any vector name of the dataset (time, frequency); quote names with special characters ("v-sweep"). AC signals are complex, so v(out)/v(in) is the transfer function.

edge is rise, fall or either; n < 0 counts crossings from the end. bandwidth drops db below the first point, by default the half-power 3.0103 dB, the same point as the f -3 dB column of the Simulation measurements (for one pole it is exactly the pole frequency). In the Simulation plot, a real-valued result on an AC dataset (such as db(v(out))) is drawn as it is rather than converted to dB again.

Examples on the rc_lowpass demo: bandwidth(v(out)/v(in)) is about 159 kHz; risetime(v(out)) on tran is the 10-90 % rise time of the filtered pulse.

Corner / Sweep Manager

Tools > Corner / Sweep Manager runs the active cell’s simulation setup over every combination of:

• Model corners: the PDK model library’s corners (none checked = the setup’s corner);
• Temperatures: a list such as -40 27 125 or a range -40:55:125 (start:step:stop); empty = the setup’s temperature;
• Variables: each with a value list. INST.param sets an instance parameter (R1.r, M1.w); any other name is a design variable that replaces {name} in the deck, for example a source’s DC value {vdd}.

The toolbar shows the number of points (at most 2000). Run Sweep runs them in parallel on every CPU core with the setup’s backend, analyses and layout parasitics.

Specs measure each point: a name, the dataset, a calculator expression that gives a number (bandwidth(v(out)), max(v(out))) and optional Min / Max limits. The results table lists every point with its spec values, green when they meet the limits and red when not, and the toolbar counts the points that meet every spec.

Overlay draws one signal or expression of every point on one plot; select a row of the table to highlight its trace. The setup is saved with the cell (sim.json).

Monte Carlo

The Monte Carlo section repeats every point Runs times with random parameter values (the same samples at every corner and temperature, reproducible with Seed). Each varied parameter has:

• Target: INST.param with * / ? wildcards in the instance name (M*.w, R?.r), or a design variable with its Nominal value;
• Sigma: a percentage of the nominal (5%) or an absolute value;
• Dist: Gauss (sigma is the standard deviation) or Uniform (sigma is the half range);
• Mismatch: draw every matching instance independently. Off, all of them share one draw per run (process variation).

With Monte Carlo results, Statistics lists mean, σ, min, max, count and yield of every spec, and a histogram of the selected spec marks the bins outside its limits in red.

Datasheet

Export datasheet… writes an HTML page of the last run: the spec summary (limits, min / mean / max / σ and yield) and the table of every point with pass / fail colours.

Optimizer

Tools > Optimizer sizes device parameters of the active cell until the specs of its Corner / Sweep Manager setup are met (at least one spec needs a Min or Max limit).

• Variables: each Target (INST.param such as M1.w, or a design variable) with Min, Max, an optional Step and Log for a log-scale search; + Variable adds one.
• Evaluations: the number of candidates to simulate.
• Goal: Best margin (the largest worst-case margin to the limits) or Least area (the smallest MOS gate area once every spec passes).
• Post-layout: place, route and extract every candidate and simulate it with its parasitics, so the specs hold after layout.

Run optimizer plots the objective of every evaluation; Stop ends the run early and Apply best to schematic writes the best values into the schematic.

Results Browser

Every successful simulation keeps the previous results: the current run is Run N, and up to 12 earlier runs are listed in Tools > Results Browser and in Compare runs above the signal list of the Simulation workspace. Rename a run (for example “pre-layout”), tick it to overlay it, or Delete it.

A ticked run is drawn dashed in the colour of each plotted signal, labelled <run>: <signal>, and gets its own rows in Measurements. A typical use is to compare the schematic with the post-layout simulation: run once, tick Include layout parasitics, run again and tick the first run.

Check Schematic

Tools > Check Schematic checks the active schematic; File > Check and Save does the same and saves the project when there are no errors. The findings appear in the Problems tab of the bottom panel (also kept up to date while you edit); click one to select its devices in the schematic.

Hierarchy Browser

Tools > Hierarchy Browser shows every layout of the project as a tree from its top cells (layouts no other layout places), with placement counts (arrays count every element). Filter finds a cell by name.

For the selected cell it shows shapes, instances, flat shapes, extent and views, the cells it places throughout its hierarchy with their total counts, and the cells that use it. Open layout / Open schematic open it. The layout editor’s Hierarchy Tree form (Edit > Hierarchy Tree, Shift+T) lists only the cells under the current cell.

Net Browser

Tools > Net Browser lists the nets of the active layout’s extraction (it extracts the nets when there is no extraction yet; Extract runs it again):

Sort by name, capacitance, area or terminals. Click a net to highlight it in the layout and zoom to it. A note warns when the layout changed after the extraction.

Layout Generators

Tools > Layout Generators (Guard Ring…, Via Array…, Matched Placement…) opens one window with four tabs. Each adds to the active layout as one step that u / Ctrl+Z undoes.

Guard Ring

Surrounds an area with a diffusion ring: a p+ substrate ring (for NMOS) or an n+ ring in nwell (for PMOS, with an nwell covering the ring and the area). The ring has its implant, optional Contacts along every side and an optional Metal1 strap. Width and Gap to area of 0 use the minimum from the layer and contact rules. Set the area in µm, or press Use selection to take the bounding box of the selected shapes and instances. With contacts and the strap, the ring is DRC clean on its own.

Via Array

Pick a via, then either:

• Every overlap of the via’s layers: a via array in each overlap of its bottom and top layers (through the hierarchy), optionally only within the area; or
• Fill the area: as many cuts as fit, centred, with enclosing pads on both layers.

Cut size, spacing and enclosure come from the via definition.

Matched Placement

Re-places matched MOS devices of the layout (for example a differential pair or a current mirror) as unit devices in a pattern:

Tick the devices, set Fingers per unit and whether to add dummy devices at both row ends. The devices must have the same type, L and finger width, and every device’s fingers must be a multiple of the unit. Each device keeps its total W; its units are named <device>.<k>, so flylines, routing and LVS still map them to the schematic device (LVS merges the parallel units). Dummies have gate, source and drain tied to the bulk net and are dropped by LVS. Neighbouring devices are moved aside to make room.

Run it before routing: wires crossing the block are not moved. Common centroid allows at most one device with an odd number of units; with single-finger devices use interdigitated, or more fingers per device.

By Example

Reuses the placement of a finished cell with the same circuit. Pick the Reference (a cell with a schematic and a placed layout) and press Place like reference: devices are matched by topology, placed where their counterparts are and sized from this cell’s schematic. Wells, implants and taps are copied; wires are not, so tick Route the flylines afterwards to route them again.

DRC Rule Designer

Tools > DRC Rule Designer (also Rule Designer… in the Rule deck section of the layout inspector) edits the technology’s DRC deck as forms instead of text.

• Start here: a step-by-step guide for people new to DRC (start from a deck, fill the gaps, fix problems, add rules, try the deck on the active cell, apply), a glossary and a picture of every kind of check.
• Rule list (left): rules grouped by layer with their values; + Rule opens a gallery of checks drawn as pictures with the question each answers, marking the ones recommended for the chosen layer; + Derived layer offers presets (transistor gates, poly outside active, wide metal) or a custom expression; Filter finds a rule.
• Design: the selected rule’s check, layers, value, name and description, with the technology’s value next to the field and a Use button when they differ. Every rule is self-tested on generated pass and fail patterns with the real DRC engine, drawn side by side, so you see that the engine accepts the limit and flags a violation one grid step inside it.
• Coverage: a matrix of which checks each layer has.
• Deck text: the generated deck.
• Issues: lint findings, such as duplicate rule names, rules that can never fire, values off the manufacturing grid, unused derived layers and routing layers without a width or space rule. Most come with a one-click fix (snap to the grid, rename, remove a redundant rule, add the missing rule); Fix automatically applies all fixes of errors and warnings and adds the missing rules.

The toolbar has Reload (the technology’s deck), Layer defaults (the deck derived from the layer and via rules), Fill gaps (adds missing width / space rules of routing layers and via enclosures with technology values), Check active cell (runs the draft deck and counts violations per rule), Apply to technology and Apply & run DRC.

Stream Layer Map

Tools > Stream Layer Map sets which GDSII / OASIS layer and datatype each technology layer is written as and read from, like a Virtuoso XStream layer map. Each row maps a stream layer / datatype to a technology layer:

• on export, a layer is written with the numbers of its first row (layers without a row keep their own numbers; Written as previews the result);
• on import, shapes on the row’s numbers go to that layer, so several stream numbers can map to one layer; (drop on import) discards them.

Load map file… reads a Virtuoso layer map (layerName purpose streamLayer streamDatatype per line, # comments); a purpose other than drawing names the layer name.purpose, namepurpose or name_purpose. Save map file… writes one, From technology starts with one row per layer, Clear removes the map. Problems (unknown layers, a number pair mapped twice, two layers written as the same numbers) are listed above the table. Apply stores the map in tech.json (stream_map).

The map applies to File > Import / Export, ics gds, ics import-gds and the MCP import_gds / export_gds tools. The project’s own library files are not affected.

Dummy Fill

Tools > Dummy Fill adds grid-aligned fill squares to a layer, to meet a density rule.

1. Pick the Fill layer. The defaults come from its rules: squares of four times the min width (at least 1 µm), spacing twice the min spacing, keepout of at least 1 µm, and the window, step and a target just above the minimum of the deck’s density rule on the layer, if there is one.
2. Set Square size, Spacing, Keepout and the layers to Avoid (fill keeps the keepout from their shapes, through the hierarchy).
3. Optionally tick Stop at a target density per window: each window is filled only up to the target, and never above the rule’s maximum.
4. Fill the Whole cell (its bounding box) or a Region in µm.
5. Preview shows the square count, the density before and after, and whether every window passes the rule; Add Fill adds the squares (undoable).

A compact cell may have no room for fill inside its bounding box; fill a larger region around it instead.

Command line (ics)

ics works on the same project folders as the desktop app. Use it for scripting, batch runs and CI; ics mcp also runs the MCP server for AI agents. The release installer puts it on the PATH. From source, build it with cargo build --release -p ics-cli (binary target/release/ics) or run it with cargo run -p ics-cli -- <args>.

• <CELL> is lib/cell or just the cell name (the first cell with that name is used).
• Exit code 0 means success. Errors print error: <message> to stderr and exit with 1.
• ics --help and ics <command> --help describe every option.

Commands

Details

Schematic from a netlist

ics schematic reads a flat SPICE netlist (R, C, L, V, I, D and M lines, and X lines for PDK MOS subcircuits) and draws it as the cell’s schematic: every pin gets a net label (node 0 or gnd gets a ground symbol) and devices are laid out in rows (PMOS, NMOS, passives, sources). Analysis lines (.op, .dc, .ac dec, .tran) and .temp set the cell’s simulation setup; other dot lines (.model, .include, .param, .ic, .meas) become its extra lines. Lengths are SPICE metres (w=2u); a bare w=2 is read as µm with a warning. The cell is created in library work unless lib/cell is given. It prints the generated deck and saves the project.

ics schematic myproj ota ota.cir && ics route myproj ota --place && ics lvs myproj ota

Simulation

ics sim uses the analyses, temperature, extra lines and backend saved for the cell in the app. --backend overrides the backend; --parasitics adds layout parasitics (also enabled when the saved setup has them on). Without --json, it prints each dataset’s title and point count, operating-point values and device regions, and the vector names of sweeps.

With --json, the full results go to stdout:

{
  "backend": "built-in",
  "elapsed_ms": 3.1,
  "datasets": [
    { "analysis": "tran", "title": "...", "vectors": { "time": [0, 1e-11], "v(out)": [0, 0.01] } }
  ]
}

AC vectors are { "re": [...], "im": [...] }.

ics spice deck.cir simulates any SPICE file with the analyses in the file (default backend built-in).

GDS

• ics import-gds adds layers the technology lacks, unless --skip-unknown-layers is given. The library name defaults to the file name. By default the library is stored as one GDS file in the project; --json stores one JSON folder per cell instead (editable, diff-friendly, larger). ics lib-storage converts an existing library between the two.
• ics gds and ics import-gds apply the technology’s stream layer map when it has one.
• ics gds-info reads a GDS file without writing anything and prints the top cells with their sizes and the read / parse / index times.

Verification and routing

• ics drc prints each rule with its violation count and up to 50 marker boxes in µm. --deck FILE uses a deck file instead of the technology’s deck. --fix first applies verified quick fixes to the cell’s top-level geometry and saves the project, then reports what is left.
• ics lvs prints the device and net pairs and the differences.
• ics route --place first places the schematic devices missing from the layout (schematic-driven layout), then routes, then saves the project.

Layout editing

• ics compact slides the cell’s top-level items toward each --dir in turn (left, right, down, up; default left,down) until the rules stop them, and saves. Fixed items stay, constraints hold and moves that would add DRC violations are undone. Symmetry constraints are first inferred from the schematic’s matched devices unless --no-infer is given.
• ics diff XORs the cell’s flattened layout per layer against the version at a git revision of the project (--rev, default HEAD) or against the same cell in another project directory (--against DIR), and prints the differences.
• ics place-like matches the cell’s devices by circuit topology to a finished reference cell (--from) and places them like it, sized from the cell’s own schematic; --route then routes it.

Optimizer

ics optimize uses the cell’s specs (sim.sweep.specs) and optimizer variables (sim.optimize), as set up in the app (Tools > Optimizer…). It prints each evaluation on stderr and the best values and spec results on stdout (--json: one object with passed, evaluations, vars and specs). --post-layout places, routes and extracts every candidate first; --apply writes the best values into the schematic and saves.

SKILL scripts

ics skill runs a Cadence SKILL (.il) file against the project (layout calls such as dbOpenCellViewByType, dbCreateRect and dbCreateInst, coordinates in µm). It prints what the script printed, lists the modified cells on stderr, and saves the project unless --no-save is given. With --json, stdout is one object:

{ "output": "...", "value": "t", "modified": ["work/inv_layout"] }

On a SKILL error it prints the script output, then error: <file>:<line>: <message>, exits with 1 and does not save.

Examples

ics new demo --template demo
ics info demo
ics netlist demo cmos_inverter
ics sim demo rc_lowpass --json > rc.json
ics sim demo nand2 --backend ngspice
ics sim demo ring_osc5 --parasitics
ics drc demo nand2 && ics lvs demo nand2
ics extract demo inv_chain
ics gds demo inv_tiles -o tiles.gds
ics import-gds demo chip.gds --lib chip
ics import-tech demo sky130A.lyp --lyt sky130A.lyt
ics skill demo make_pads.il --json
ics drc demo cmos_inverter --fix
ics diff demo nand2 --rev HEAD~1

A CI check of a cell:

ics drc myproj work/opamp && ics lvs myproj work/opamp

MCP server for AI agents

ics mcp (the mcp command of the ics command line tool) exposes IC Studio to AI agents through the Model Context Protocol (stdio). An agent can create and open projects, read netlists, simulate, edit layouts, generate and route layout from a schematic, and run DRC, extraction and LVS.

Setup

The release installer registers the server with Claude Code when claude is on the PATH. In the app, File > Settings… > AI agents (MCP) has Add to Claude Code, which does the same, and Copy MCP config, which copies the JSON below for other clients.

To register it by hand:

claude mcp add --scope user ic-studio -- /path/to/ics mcp

For other MCP clients, add a stdio server whose command is the ics binary with the argument mcp:

{ "mcpServers": { "ic-studio": { "command": "/path/to/ics", "args": ["mcp"] } } }

From source, build it with cargo build --release -p ics-cli and use target/release/ics.

Then ask, for example: “create a demo project in ./demo and run LVS on cmos_inverter”.

Agent skill

The tools tell an agent what it can do; the ic-studio skill in skills/ic-studio tells it how to design with them: the schematic → simulation → layout → DRC → LVS → post-layout flow, units, how to read LVS / DRC results, the schematic.json format and the ics CLI as a fallback. Install it with:

npx skills add geniuskey/ic-studio

or copy skills/ic-studio into ~/.claude/skills/.

Conventions

• Coordinates are in µm, y pointing up, snapped to the technology grid.
• A cell argument is a cell name or lib/cell. Layout edit tools create the cell (in library work) and its layout view if they do not exist.
• Edits stay in memory until save_project.

Tools

The server has 34 tools:

run_skill

run_skill takes either code (SKILL source) or file (a .il path, also the base of relative load() paths) and returns the following. The optional cell names the cell that geGetEditCellView() returns.

{ "output": "what the script printed", "value": "value of the last form", "modified": ["work/pads"] }

On a SKILL error the tool fails with SKILL error: <file or line>: <message>, followed by the cells already modified (their edits are kept) and the output printed so far. In live mode the app records undo history for every changed layout and opens the first one when no cell is open.

Live mode

While the desktop app is running, the MCP server (ics mcp) forwards every tool call to it, and the agent works on the project open in the window:

• edits appear immediately and layout edits can be undone with Ctrl+Z,
• the window opens the affected cell in the matching workspace; simulate shows the waveforms, and DRC / extraction / LVS results appear in the layout panels with markers,
• the status bar shows MCP live, and each call is logged in the console as MCP · <tool> <cell> -> <summary>.

The app listens on 127.0.0.1 with a per-session token and writes the discovery file live.json to %LOCALAPPDATA%\ic-studio (Windows) or $XDG_RUNTIME_DIR/ic-studio, falling back to ~/.local/state/ic-studio (Linux, macOS). ics mcp checks for a running app on every call, so you can start or close the app at any time.

Without a running app, or with ICS_MCP_STANDALONE=1, the server works on its own in-memory project; start with open_project or new_project. ICS_LIVE_DIR overrides the folder of the discovery file.

Keyboard shortcuts

Ctrl on Windows and Linux is Cmd on macOS. Press F1 in the app to show this list. Canvas keys work while the mouse is over the canvas and no text field has focus.

General

Canvas (schematic and layout)

The mouse follows the Interaction profile in Settings (Ctrl+,). Virtuoso (the default) matches the Virtuoso defaults: the wheel pans, Ctrl+wheel zooms at the mouse and a right drag zooms into a box. Conventional zooms with the wheel and pans with a right drag. Bindkeys are the same in both.

Schematic

Layout

Layout keys follow the Cadence Virtuoso (IC6) default bindkeys.

Ctrl+Z stays undo, as in the rest of the application (Virtuoso binds it to zoom in).

Simulation plots

Scroll to zoom, drag to pan, double-click to reset the view. Hover a trace to read its value.