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Open-source · full-custom IC design

From schematic to sign-off,
in one native app.

IC Studio puts schematic capture, SPICE simulation, layout, automatic place and route, DRC, LVS and parasitic extraction on one design database. Draw a circuit, generate its layout, verify it and simulate it again with the parasitics, without leaving the window or converting a single file.

Auto place and route: a 28-transistor full adder generated from its schematic, LVS clean

28Tfull adder placed and routed automatically, DRC and LVS clean
8,192inverters (about 250k shapes) browsed interactively
3front ends on one core: desktop app, CLI, MCP for AI agents
3 OSWindows, Linux and macOS, GPU rendered with wgpu

One database, the whole loop

Most open-source flows chain separate tools through netlists and GDS files. In IC Studio the schematic, the simulator and the layout share one design database, so every step knows about the others:

Schematic→ Simulate→ Generate layout→ Route→ DRC · LVS→ Extract parasitics→ Simulate again ↺
  • Layouts are generated from schematics and routed automatically.
  • Layouts are checked against schematics (LVS) with clickable differences.
  • Parasitics extracted from the layout flow straight back into simulation.

What you get

SCH

Schematic and simulation

Live connectivity, operating-point annotation, DC / AC / transient analyses on a built-in simulator or ngspice, Bode plots and automatic measurements.

P&R

Automatic place and route

Transistors placed as PCells with shared diffusion, common-centroid matching and dummies; a rip-up-and-reroute maze router wires every net DRC-clean.

LAY

Hierarchical layout

Instances and arrays, level-of-detail rendering for large designs, Boolean layer operations, vias, PCells, GDSII and OASIS in and out.

DRC

Verification

Rule-deck DRC with derived layers, connectivity extraction, LVS with device merging, and sign-off runs through KLayout, Calibre or netgen.

ADE

Analysis tools

A waveform calculator, corner, parametric and Monte Carlo sweeps with specs, yield and datasheets, and run-to-run comparison of results.

GEN

Layout generators

Guard rings, via arrays, common-centroid matched placement and density fill, plus a visual DRC rule designer and Virtuoso-compatible SKILL.

PDK

Real PDKs

Start on the generic 180 nm technology, then switch to SKY130 or IHP SG13G2: layers, device recognition, models and corners from one PDK file.

AI

Scriptable and agent-ready

Every action is a command. The ics CLI runs in CI, and the MCP server lets an AI agent design in the window you are watching.

Try it in one minute

git clone https://github.com/geniuskey/ic-studio
cd ic-studio
cargo run --release -- --demo --cell full_adder --workspace layout

With a release installed, run ic-studio --demo --cell full_adder --workspace layout instead. The demo project opens on an automatically placed and routed full adder. The demo gallery walks through every example and has ready-made scripts for presenting IC Studio live.

What is in the box

Two programs, installed together:

ProgramPurpose
ic-studioThe desktop application
icsCommand-line interface for scripting and CI
ics mcpThe same ics program run as a Model Context Protocol server for AI agents

All three front ends use the same core library, so a project edited in the app can be simulated, checked or exported from the command line, or driven by an agent.

Main concepts

  • Project: a folder holding ic-studio.json, the technology (tech.json) and one folder per library. Everything is human-readable JSON that diffs well in git.
  • Library: a named group of cells (the demo project has work and pcells).
  • Cell: a design unit with up to three views: schematic, simulation (the analyses set up for the schematic) and layout.
  • Workspace: the app has four workspaces, Home, Schematic, Simulation and Layout. The open cells appear as tabs shared by all workspaces; switching workspace shows the same cell in a different view.
  • Technology (PDK): layers, GDS numbers, display styles, design rules and electrical coefficients. New projects start with a generic 180 nm-class technology.

How to read this guide

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